1. Field of the Invention
The present invention relates to silicon carbide semiconductor devices, and particularly to a termination structure including a junction termination extension (JTE) or a field limiting ring (FLR) for semiconductor elements.
2. Description of the Background Art
Semiconductor devices using silicon carbide (SiC) (MOSFETs (Metal oxide semiconductor field effect transistors), IGBTs (Insulated Gate Bipolar Transistors) etc.) are holding great promise as next-generation switching elements realizing high withstand voltage, low loss and high heat resistance, and they are expected for applications to power semiconductor devices such as inverters. Also, as a characteristic of SiC, it is known that the diffusion coefficients of impurities are very small, and ion-implanted impurities hardly diffuse even when thermally processed, and the impurity concentration profile immediately after the ion implantation is almost maintained.
Termination structures provided in the periphery (termination) of semiconductor elements include the JTE (Junction Termination Extension; for example, see B. Jayant Baliga “Power Semiconductor Devices” PWS Publishing Company, 1995, pp. 111-113.) The JTE alleviates the electric field strength at the termination of semiconductor elements and improves the withstand voltage of the elements. In conventional SiC semiconductor device manufacturing methods, the ion implantation for the formation of the JTE region is carried out in multiple stages with varying implant energies (see FIG. 2). This is for the purpose of forming a JTE region with a Box type impurity concentration profile in SiC where impurity is not likely to diffuse.
After the formation of the JTE region by ion implantation, activation annealing is needed to activate the impurity; during the activation annealing, a damage layer is formed in the surface of the JTE region. Accordingly, after the activation annealing, the damage layer must be removed by sacrificial oxidation or dry etching. Accordingly, the JTE region has to be formed such that the designed withstand voltage is obtained after the surface damage layer has been removed.
Thus, the JTE region has to be formed such that a desired withstand voltage is obtained after the surface damage layer formed by activation annealing has been removed. In other words, the amount of removal of the surface of the JTE region must be determined such that the desired withstand voltage is obtained. In conventional SiC semiconductor device manufacturing methods, the margin of the amount of etching of the JTE region surface (the range of the amount of etching in which a desired withstand voltage is obtained) was small, and highly precise control of the amount of etching was needed in order to obtain the desired withstand voltage.